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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Data Sheet July 1999 File Number
3948.5
0.3A, 60V, 6 Ohm, ESD Rated, Current Limited, Voltage Clamped, Logic Level N-Channel Power MOSFETs
These are intelligent monolithic power circuits which incorporate a lateral bipolar transistor, resistors, zener diodes and a power MOS transistor. The current limiting of these devices allow it to be used safely in circuits where a shorted load condition may be encountered. The drain to source voltage clamping offers precision control of the circuit voltage when switching inductive loads. The "Logic Level" gate allows this device to be fully biased on with only 5V from gate to source, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. These devices incorporate ESD protection and are designed to withstand 2kV (Human Body Model) of ESD. Formerly developmental type TA49028.
Features
* 0.30A, 60V * rDS(ON) = 6.0 * Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC * Built in Voltage Clamp * Temperature Compensating PSPICE(R) Model * 2kV ESD Protected * Controlled Switching Limits EMI and RFI * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER RLD03N06CLE RLD03N06CLESM RLP03N06CLE PACKAGE TO-251AA TO-252AA TO-220AB BRAND 03N06C 03N06C 03N06CLE
S G
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A.
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (FLANGE)
6-418
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE 60 60 +5.5 Self Limited 30 0.2 2 -55 to 175 300 260 UNITS V V V W W/oC KV oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . .ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) IDS(LIMIT) tON td(ON) tr td(OFF) tf tOFF CISS COSS CRSS RJC RJA TO-220 Package TO-251 and TO-252 Packages VDS = 25V, VGS = 0V, f = 1MHz TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 45V, VGS = 0V VGS = 5V ID = 0.100A, VGS = 5V VDS = 15V, VGS = 5V TJ = 25oC TJ = 150oC TJ = 25oC TJ = 150oC TJ = 25oC TJ = 150oC TJ = 25oC TJ = 150oC MIN 60 1 280 140 TYP 100 65 3.0 MAX 85 2.5 25 250 5 20 6.0 12.0 420 210 7.5 2.5 5.0 7.5 5.0 12.5 5.0 80 100 UNITS V V A A A A mA mA s s s s s s pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Limiting Current
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDD = 30V, ID = 0.10A, RL = 300, VGS = 5V, RGS = 25
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 300s maximum, duty cycle = 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr TEST CONDITIONS ISD = 0.1A ISD = 0.1A, dISD/dt = 100A/s MIN TYP MAX 1.5 1.0 UNITS V ms
6-419
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) ID , DRAIN CURRENT (A)
Unless Otherwise Specified
1
TC = 25oC, TJ = MAX RATED OPERATION IN THIS AREA IS LIMITED BY JUNCTION TEMPERATURE
DC
25oC 175oC
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
2 1 ZJC , NORMALIZED THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 PDM
0.01 10-5
NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
I(CLAMP) , CLAMPED DRAIN CURRENT (A)
1
ID , DRAIN CURRENT (A)
TC = 25oC TEMPERATURES LISTED ARE STARTING JUNCTION TEMPERATURES
0.40
VGS = 5V
VGS = 7.5V VGS = 4V
0.30 VGS = 3V 0.20
25oC 50oC 75oC 100oC 150oC 0.1 0.001 0.01 0.1 tAV, TIME IN CLAMP (s) 1 125oC 10
0.10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 0 1 2 3 4 5 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. SELF-CLAMPED INDUCTIVE SWITCHING
FIGURE 5. SATURATION CHARACTERISTICS
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
ID(ON) , ON STATE DRAIN CURRENT (A) 0.60 0.50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 15V PULSE TEST PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -55oC
Unless Otherwise Specified (Continued)
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 0.10A
2.0
0.40 0.30 0.20
25oC
1.5
1.0
175oC 0.10 0 0 1 2 3 4 VGS , GATE TO SOURCE VOLTAGE (V) 5
0.5
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 6. TRANSFER CHARACTERISTICS
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0
VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
2.0
ID = 10mA
NORMALIZED GATE THRESHOLD VOLTAGE
1.5
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0
40
80
120
160
200
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE
NORMALIZED DRAIN LIMITING CURRENT
300 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 200
2.0 VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 1.5
C, CAPACITANCE (pF)
1.0
CISS 100 COSS
0.5
CRSS 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 11. NORMALIZED DRAIN LIMITING CURRENT vs JUNCTION TEMPERATURE
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
60 VDS , DRAIN SOURCE VOLTAGE (V)
Unless Otherwise Specified (Continued)
5.00 VGS , GATE SOURCE VOLTAGE (V)
45 VDD = BVDSS 30 0.75 BVDSS 15 0.50 BVDSS 0.25 BVDSS RL = 600 IG(REF) = 0.1mA VGS = 5V
3.75
2.50
1.25
0
0.00
10 --------------------I G ( ACT )
I G ( REF )
t, TIME (s)
--------------------40 I G ( ACT )
I G ( REF )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT.
Test Circuits and Waveforms
VDD tON td(ON) tr VDS VDS 90% tOFF td(OFF) tf 90%
RL
VGS 10% DUT 0V VGS RGS 10% 50% PULSE WIDTH 50% 90% 10%
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
Detailed Description
Temperature Dependence of Current Limiting and Switching Speed Performance
The RLD03N06CLE, CLESM and RLP03N06CLE are monolithic power devices which incorporate a Logic Level power MOSFET transistor with a current sensing scheme and control circuitry to enable the device to self limit the drain source current flow. The current sensing scheme supplies current to a resistor that is connected across the base to emitter of a bipolar transistor in the control section. The collector of this bipolar transistor is connected to the gate of the power MOSFET transistor. When the ratiometric current from the current sensing reaches the value required to forward bias the base emitter junction of this bipolar transistor, the bipolar "turns on". A resistor is incorporated in series with the gate of the power MOSFET transistor allowing the bipolar transistor to adjust the drive on the gate of the power MOSFET transistor to a voltage which then maintains a constant current in the power MOSFET transistor. Since both the ratiometric current sensing scheme and the base emitter unction
voltage of the bipolar transistor vary with temperature, the current at which the device limits is a function of temperature. This dependence is shown in Figure 3. The resistor in series with the gate of the power MOSFET transistor also results in much slower switching performance than in standard power MOSFET transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable.
DC Operation
The limit on the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown in the equation below. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore, be expressed as shown in Equation 1:
( 150C - T AMBIENT ) DS = ------------------------------------------------------I LM * ( RJC + RJA ) (EQ.1)
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
The results of this equation are plotted in Figure 15 for various heatsinks. These values are plotted as Figures 16 through 21 for various heatsink thermal resistances.
Duty Cycle Operation
In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLD03N06CLE, CLESM and RLP03N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less then 1ms, the temperature of the header can be considered a constant, thereby the junction temperature can be calculated simply as shown in Equation 2:
T C = ( V DS * I D * D * R CA ) + T AMBIENT (EQ.2)
Limited Time Operations
Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 ms, thereby the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as Figures 22 through 25 (RLP03N06CLE) and Figure 26 through 29 (RLD03N06CLE and RLD03N06CLESM) give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur.
Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated in Equation 2, the expression for maximum VDS under duty cycle operation is shown in Equation 3
:
o 150 C - T C V DS = ----------------------------------------I LM * D * R JC
(EQ.3)
Typical Performance Curves
90 VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , APPLIED VOLTAGE (V) 75 HSTR = 5oC/W 60 HSTR = 10oC/W 45 30 HSTR = 0oC/W HSTR = 1oC/W HSTR = 2oC/W TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W 90 DC = 50% 75 60 45 30 TJ = 175oC ILIM = 0.210A 15 RJC = 5.0oC/W DUTY CYCLE = DC MAX PULSE WIDTH = 100ms 0 100 125 150 TA , AMBIENT TEMPERATURE (oC) DC = 20% DC = 2% DC = 5% DC = 10%
HSTR = 25oC/W
15 HSTR = 80oC/W 0
25
50
75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
175
175
NOTE: Heat Sink Thermal Resistance = HSTR. FIGURE 15. DC OPERATION IN CURRENT LIMITING
90 VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 2% 75 DC = 50% 60 45 30 15 0 100 DC = 20% DC = 5% DC = 10%
FIGURE 16. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HEATSINK THERMAL RESISTANCE = 1oC/W)
90 VDS , DRAIN TO SOURCE VOLTAGE (V) DC = 20% 75 60 DC = 50% 45 30 15 0 75 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W DUTY CYCLE = DC MAX PULSE WIDTH = 100ms 175 100 125 150 TA , AMBIENT TEMPERATURE (oC) DC = 2% DC = 5% DC = 10%
TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W DUTY CYCLE = DC MAX PULSE WIDTH = 100ms 175
125 150 TA , AMBIENT TEMPERATURE (oC)
FIGURE 17. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 2oC/W)
FIGURE 18. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 5oC/W)
6-423
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
VDS , DRAIN TO SOURCE VOLTAGE (V) 90 DC = 20% 75 DC = 50% 60 45 30 15 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W DUTY CYCLE = DC DC = 5% DC = 10% DC = 2% VDS , DRAIN TO SOURCE VOLTAGE (V)
(Continued)
90 DC = 20% 75 DC = 5% 60 45 DC = 50% 30 15 0 TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W DUTY CYCLE = DC 25 50 DC = 10% DC = 2%
MAX PULSE WIDTH = 100ms
MAX PULSE WIDTH = 100ms 175
75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
FIGURE 19. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 10oC/W)
90 75 60 45 30 DC = 50% 15 0 DC = 20% DC = 10% DC = 5% TJ = 175oC ILIM = 0.210A RJC = 5.0oC/W DC = 2% DC = 1%
FIGURE 20. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 25oC/W)
10 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC
VDS , DRAIN TO SOURCE VOLTAGE (V)
8 TIME TO 175oC (s) 175
6
4
2
25
50
75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
0
10
NOTE:
Duty Cycyle = DC, Max Pulse Width = 100ms.
30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 21. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 80oC/W)
FIGURE 22. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC)
10
10 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC
8 TIME TO 175oC (s)
8 TIME TO 175oC (s) STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC 2 STARTING TJ = 150oC
6
4
4
2
0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90
0
10
50 70 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 23. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC)
FIGURE 24. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC)
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
10
(Continued)
10
STARTING TJ = 75oC
8 TIME TO 175oC (s) TIME TO 175oC (s) STARTING TJ = 100oC
8 STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC
6
4
STARTING TJ = 125oC
4
2 STARTING TJ = 150oC 0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90
2
0
10
30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V)
90
FIGURE 25. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC)
10
FIGURE 26. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC)
10
8 TIME TO 175oC (s)
TIME TO 175oC (s)
6
STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC
8 STARTING TJ = 75oC 6 STARTING TJ = 100oC STARTING TJ = 125oC 2 STARTING TJ = 150oC
4
4
2
0
0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90
10
30
50
70
90
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 27. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC)
10
FIGURE 28. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC)
STARTING TJ = 75oC 8 TIME TO 175oC (s)
6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 STARTING TJ = 150oC 10 30 50 70 90
0
VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 29. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC)
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE PSPICE Electrical Model
SUBCKT RLD03N06CLE 2 1 3; CA 12 8 0.547e-9 CB 15 14 0.547e-9 CIN 6 8 0.301e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 20 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.96e-9 LSOURCE 3 7 2.96e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 QCONTROL 20 70 7 QMOD 1 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1.123 RGATE 9 20 3200 RIN 6 8 1e9 RSOURCE1 8 70 RDSMOD 1.12 RSOURCE2 70 7 RSMOD 2.16 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.22 .MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7) .MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL QMOD NPN (BF =5) .MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8) .MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6) .MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6) .MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.
12 S1B CA EGS
rev 4/18/94
5 DRAIN LDRAIN 2
DBREAK
10 11 +
DPLCAP
EBREAK
17 18 EVTO + 18 8
6 8 +
ESG 16 VTO +
RDRAIN
DBODY
GATE 1 LGATE DESD1 91 DESD2
RGATE 9
21 6 RIN CIN 8 MOS1
MOS2
RSOURCE1 RSOURCE2 70 7
LSOURCE 3 SOURCE
S1A 13 8 13 + 6 8 14 13
S2A 15 S2B CB + EDS 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT +
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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